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 HEF4543B
BCD to 7-segment latch/decoder/driver
Rev. 05 -- 27 October 2009 Product data sheet
1. General description
The HEF4543B is a BCD to 7-segment latch/decoder/driver for liquid crystal and LED displays. It has four address inputs (D0 to D3), an active LOW latch enable input (LE), an active HIGH blanking input (BL), an active HIGH phase input (PH) and seven buffered segment outputs (Qa to Qg). The circuit provides the function of a 4-bit storage latch and an 8-4-2-1 BCD to 7-segment decoder/driver. It can invert the logic levels of the output combination. The phase (PH), blanking (BL) and latch enable (LE) inputs are used to reverse the function table phase, blank the display and store a BCD code, respectively. For liquid crystal displays, a square-wave is applied to PH and the electrical common back-plane of the display. The outputs of the device are directly connected to the segments of the liquid crystal. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input. It is also suitable for use over the full industrial (-40 C to +85 C) temperature range.
2. Features
I I I I I Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Operates across the full industrial temperature range -40 C to +85 C Complies with JEDEC standard JESD 13-B
3. Applications
I Industrial
4. Ordering information
Table 1. Ordering information All types operate from -40 C to +85 C Type number HEF4543BP HEF4543BT Package Name DIP16 SO16 Description plastic dual in-line package; 16-leads (300 mil) plastic small outline package; 16 leads; body width 3.9 mm Version SOT38-4 SOT109-1
NXP Semiconductors
HEF4543B
BCD to 7-segment latch/decoder/driver
5. Functional diagram
5 D0 1 LE 3 D1 LATCHES 2 D2 4 D3
7 BL
DECODER
6 PH
DRIVERS Qg 14 Qf 15 Qe 13 Qd 12 Qc 11 Qb 10 Qa 9
001aae742
Fig 1.
Functional diagram
HEF4543B_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 27 October 2009
2 of 16
NXP Semiconductors
HEF4543B
BCD to 7-segment latch/decoder/driver
BL
D0
Qa
D1 Qb
Qc
D2 Qd
Qe
D3 Qf
Qg
LE
PH
001aae744
Fig 2.
Logic diagram
HEF4543B_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 27 October 2009
3 of 16
NXP Semiconductors
HEF4543B
BCD to 7-segment latch/decoder/driver
6. Pinning information
6.1 Pinning
HEF4543B
LE D2 D1 D3 D0 PH BL VSS 1 2 3 4 5 6 7 8
001aae743
16 VDD 15 Qf 14 Qg 13 Qe 12 Qd 11 Qc 10 Qb 9 Qa
Fig 3.
Pin configuration
6.2 Pin description
Table 2. Symbol LE D0 to D3 PH BL VSS Qa to Qg VDD Pin description Pin 1 5, 3, 2, 4 6 7 8 9, 10, 11, 12, 13, 15, 14 16 Description latch enable input (active LOW) address (data) input phase input (active HIGH) blanking input (active HIGH) ground supply voltage segment output supply voltage
HEF4543B_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 27 October 2009
4 of 16
NXP Semiconductors
HEF4543B
BCD to 7-segment latch/decoder/driver
7. Functional description
Table 3. Inputs LE X H H H H H H H H H H H H L BL H L L L L L L L L L L L L L PH L L L L L L L L L L L L L L H
[2]
Function table [1] Outputs D3 X L L L L L L L L H H H H X D2 X L L L L H H H H L L L H X D1 X L L H H L L H H L L H X X D0 X L H L H L H L H L H X X X Qa L H L H H L H H H H H L L n.c. inverse of above Qb L H H H H H L L H H H L L Qc L H H L H H H H H H H L L Qd L H L H H L H H L H H L L Qe L H L H L L L H L H L L L Qf L H L L L H H H L H H L L Qg L L L H H H H H L H H L L Display blank 0 1 2 3 4 5 6 7 8 9 blank blank n.c as above
as above
[1] [2]
as above
H = HIGH voltage level; L = LOW voltage level; X = don't care,: n.c. = no change. For liquid crystal displays, apply a square-wave to PH; For common cathode LED displays, select PH = LOW; For common anode LED displays, select PH = HIGH.
a f e g d b c
001aaj494
Fig 4.
Seven segment digital display with segment designation
8. Limiting values
Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD VI II/O Tstg Tamb
HEF4543B_5
Parameter supply voltage input voltage input/output current storage temperature ambient temperature
Conditions
Min -0.5 -0.5 -65 -40
Max +18 VDD + 0.5 10 +150 +85
Unit V V mA C C
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 27 October 2009
5 of 16
NXP Semiconductors
HEF4543B
BCD to 7-segment latch/decoder/driver
Table 4. Limiting values ...continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Ptot P
[1] [2]
Parameter total power dissipation power dissipation
Conditions DIP16 package SO16 package per output
[1] [2]
Min -
Max 750 500 100
Unit mW mW mW
For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C. For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
9. Recommended operating conditions
Table 5. Symbol VDD VI Tamb t/V Recommended operating conditions Parameter supply voltage input voltage ambient temperature input transition rise and fall rate in free air VDD = 5 V VDD = 10 V VDD = 15 V Conditions Min 3 0 -40 Typ Max 15 VDD +85 3.75 0.5 0.08 Unit V V C s/V s/V s/V
10. Static characteristics
Table 6. Static characteristics VSS = 0 V; VI = VSS or VDD unless otherwise specified. Symbol Parameter VIH HIGH-level input voltage Conditions |IO| < 1 A VDD 5V 10 V 15 V VIL LOW-level input voltage |IO| < 1 A 5V 10 V 15 V VOH HIGH-level output voltage 5V 10 V 15 V VOL LOW-level output voltage |IO| < 1 A 5V 10 V 15 V IOH HIGH-level output current VO = 2.5 V VO = 4.6 V VO = 9.5 V VO = 13.5 V 5V 5V 10 V 15 V Tamb = -40 C Min 3.5 7.0 11.0 4.95 9.95 14.95 -1.7 -0.52 -1.3 -3.6 Max 1.5 3.0 4.0 0.05 0.05 0.05 Tamb = 25 C Min 3.5 7.0 11.0 4.95 9.95 14.95 -1.4 -0.44 -1.1 -3.0 Max 1.5 3.0 4.0 0.05 0.05 0.05 Tamb = 85 C Min 3.5 7.0 11.0 4.95 9.95 14.95 -1.1 -0.36 -0.9 -2.4 Max 1.5 3.0 4.0 0.05 0.05 0.05 V V V V V V V V V V V V mA mA mA mA Unit
HEF4543B_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 27 October 2009
6 of 16
NXP Semiconductors
HEF4543B
BCD to 7-segment latch/decoder/driver
Table 6. Static characteristics ...continued VSS = 0 V; VI = VSS or VDD unless otherwise specified. Symbol Parameter IOL LOW-level output current Conditions VO = 0.4 V VO = 0.5 V VO = 1.5 V II IDD input leakage current supply current IO = 0 A VDD 5V 10 V 15 V 15 V 5V 10 V 15 V CI input capacitance Tamb = -40 C Min 0.52 1.3 3.6 Max 0.3 20 40 80 Tamb = 25 C Min 0.44 1.1 3.0 Max 0.3 20 40 80 7.5 Tamb = 85 C Min 0.36 0.9 2.4 Max 1.0 150 300 600 mA mA mA A A A A pF Unit
11. Dynamic characteristics
Table 7. Dynamic characteristics VSS = 0 V; Tamb = 25 C; For test circuit see Figure 7;unless otherwise specified. Symbol tPHL Parameter HIGH to LOW propagation delay Conditions Dn to Qn; see Figure 5 VDD 5V 10 V 15 V LE to Qn; see Figure 5 5V 10 V 15 V BL to Qn; see Figure 5 5V 10 V 15 V tPLH LOW to HIGH propagation delay Dn to Qn; see Figure 5 5V 10 V 15 V LE to Qn; see Figure 5 5V 10 V 15 V BL to Qn; see Figure 5 5V 10 V 15 V tt transition time pin Qn; see Figure 5 5V 10 V 15 V tsu set-up time Dn to LE; see Figure 6 5V 10 V 15 V Extrapolation formula[1] 153 ns + (0.55 ns/pF) CL 64 ns + (0.23 ns/pF) CL 47 ns + (0.16 ns/pF) CL 143 ns + (0.55 ns/pF) CL 69 ns + (0.23 ns/pF) CL 52 ns + (0.16 ns/pF) CL 118 ns + (0.55 ns/pF) CL 54 ns + (0.23 ns/pF) CL 37 ns + (0.16 ns/pF) CL 153 ns + (0.55 ns/pF) CL 64 ns + (0.23 ns/pF) CL 47 ns + (0.16 ns/pF) CL 163 ns + (0.55 ns/pF) CL 69 ns + (0.23 ns/pF) CL 52 ns + (0.16 ns/pF) CL 98 ns + (0.55 ns/pF) CL 54 ns + (0.23 ns/pF) CL 32 ns + (0.16 ns/pF) CL 10 ns + (1.00 ns/pF) CL 9 ns + (0.42 ns/pF) CL 6 ns + (0.28 ns/pF) CL Min 40 20 15 Typ 180 75 55 170 80 60 145 65 45 180 75 55 190 80 60 125 55 40 60 30 20 20 5 0 Max 360 150 110 340 160 120 290 130 90 360 150 110 380 160 120 250 110 80 120 60 40 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
HEF4543B_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 27 October 2009
7 of 16
NXP Semiconductors
HEF4543B
BCD to 7-segment latch/decoder/driver
Table 7. Dynamic characteristics ...continued VSS = 0 V; Tamb = 25 C; For test circuit see Figure 7;unless otherwise specified. Symbol th Parameter hold time Conditions Dn to LE; see Figure 6 VDD 5V 10 V 15 V tW pulse width pin LE HIGH; minimum width; see Figure 6 5V 10 V 15 V Extrapolation formula[1] Min 0 15 20 60 30 20 Typ -15 0 5 30 15 10 Max Unit ns ns ns ns ns ns
[1]
The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).
Table 8. Dynamic power dissipation PD PD can be calculated from the formulas shown. VSS = 0 V; tr = tf 20 ns; Tamb = 25 C. Symbol PD Parameter dynamic power dissipation VDD 5V 10 V 15 V Typical formula for PD (W) PD = 2200 x fi + (fo x CL) x VDD2 PD = 10400 x fi + (fo x CL) x VDD PD = 33000 x fi + (fo x CL) x VDD
2 2
where: fi = input frequency in MHz, fo = output frequency in MHz, CL = output load capacitance in pF, VDD = supply voltage in V, (CL x fo) = sum of the outputs.
12. Waveforms
VI LE VSS VI D2 VSS VI LT VSS tPHL VI BL VSS tPLH tPHL VOH Qg VOL tTHL 90 % VM 10 % tTLH
001aaj496
VM
VM
VM
VM
tPLH tPHL tPHL
tPLH
tPLH
Conditions: D3 = LOW and D0 = D1 =HIGH.
Fig 5.
Propagation delays and output transitions times
HEF4543B_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 27 October 2009
8 of 16
NXP Semiconductors
HEF4543B
BCD to 7-segment latch/decoder/driver
VI LE input VSS tW VI D2 input VSS tsu th VOH Qg output VOL
001aaj799
VM
VM
Conditions: D3 = BL = LOW; D0 = D1 = LE = HIGH
Fig 6.
Waveforms showing minimum LE pulse width, set-up, and hold time for DC to LE
HEF4543B_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 27 October 2009
9 of 16
NXP Semiconductors
HEF4543B
BCD to 7-segment latch/decoder/driver
VI negative pulse 0V
tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW
001aaj781
VM
VI positive pulse 0V
VM
a. Input waveforms
VDD VI G
RT
VO DUT
CL
001aag182
b. Test circuit
Test data is given in Table 9. Definitions for test circuit: RL = Load resistance; CL = Load capacitance including jig and probe capacitance; RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
Fig 7. Table 9.
Test circuit for switching times Test data Input VI VM 0.5VI tr, tf 20 ns VDD Load CL 50 pF
Supply voltage 5 V to 15 V
13. Application information
Some examples of applications for the HEF4543B are:
* * * * *
Driving LCD displays Driving LED displays Driving fluorescent displays Driving incandescent displays Driving gas discharge displays
HEF4543B_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 27 October 2009
10 of 16
NXP Semiconductors
HEF4543B
BCD to 7-segment latch/decoder/driver
VDD
common anode LED
HEF4543B
output PH VSS PH VDD
001aae746
common cathode LED
HEF4543B
output
001aae745
a. common cathode
b. common anode
Bipolar transistors may be added for gain where VDD 10 V or IO 10 mA.
Fig 8.
Connection to LED display readout
appropriate voltage
HEF4543B
output PH one of seven segments common back-plane
HEF4543B
output PH VSS
square wave; VSS to VDD
001aae747
001aae748
Fig 9.
Connection to LCD readout
Fig 10. Connection to incandescent display readout
appropriate voltage
HEF4543B
output
HEF4543B
PH output PH VSS
001aae749
VSS
to filament supply VSS or appropriate voltage below VSS
001aae750
Fig 11. Connection to gas discharge display readout
Fig 12. Connection to fluorescent display readout
HEF4543B_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 27 October 2009
11 of 16
NXP Semiconductors
HEF4543B
BCD to 7-segment latch/decoder/driver
14. Package outline
DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4
D seating plane
ME
A2
A
L
A1
c Z e b1 b 16 9 b2 MH wM (e 1)
pin 1 index E
1
8
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.02 A2 max. 3.2 0.13 b 1.73 1.30 0.068 0.051 b1 0.53 0.38 0.021 0.015 b2 1.25 0.85 0.049 0.033 c 0.36 0.23 0.014 0.009 D (1) 19.50 18.55 0.77 0.73 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.1 e1 7.62 0.3 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 0.76 0.03
Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT38-4 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION
ISSUE DATE 95-01-14 03-02-13
Fig 13. Package outline SOT38-4 (DIP16)
HEF4543B_5 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 27 October 2009
12 of 16
NXP Semiconductors
HEF4543B
BCD to 7-segment latch/decoder/driver
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A X
c y HE vMA
Z 16 9
Q A2 pin 1 index Lp 1 e bp 8 wM L detail X A1 (A 3) A
0
2.5 scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 10.0 9.8 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 0.039 0.016 Q 0.7 0.6 0.028 0.020 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3
0.010 0.057 0.069 0.004 0.049
0.019 0.0100 0.39 0.014 0.0075 0.38
0.244 0.041 0.228
0.028 0.004 0.012
8 o 0
o
Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT109-1 REFERENCES IEC 076E07 JEDEC MS-012 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 14. Package outline SOT109-1 (SO16)
HEF4543B_5 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 27 October 2009
13 of 16
NXP Semiconductors
HEF4543B
BCD to 7-segment latch/decoder/driver
15. Abbreviations
Table 10. Acronym DUT Abbreviations Description Device Under Test
16. Revision history
Table 11. Revision history Release date 20091027 Data sheet status Product data sheet Change notice Supersedes HEF4543B_4 Document ID HEF4543B_5 Modifications:
* * *
Section 2 "Features" ESD entry removed. Section 9 "Recommended operating conditions" t/V values updated. Section 15 "Abbreviations" ESD entries removed. Product data sheet Product specification Product specification HEF4543B_CNV_3 HEF4543B_CNV_2 -
HEF4543B_4 HEF4543B_CNV_3 HEF4543B_CNV_2
20090317 19950101 19950101
HEF4543B_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 27 October 2009
14 of 16
NXP Semiconductors
HEF4543B
BCD to 7-segment latch/decoder/driver
17. Legal information
17.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
17.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
18. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
HEF4543B_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 27 October 2009
15 of 16
NXP Semiconductors
HEF4543B
BCD to 7-segment latch/decoder/driver
19. Contents
1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 17 17.1 17.2 17.3 17.4 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Application information. . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information. . . . . . . . . . . . . . . . . . . . . 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 27 October 2009 Document identifier: HEF4543B_5


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